The present invention relates to a memory system including a program/erase (PE) count circuit and a method of operating the same.
The assignee of the present patent application has focused its attention to resistive memory cells, believing its use as a resistive random-access memory (RRAM) could be an excellent candidate for ultra-high density non-volatile information storage. A typical resistive memory cell studied has an insulator layer provided between a pair of electrodes and exhibits electrical pulse induced hysteretic resistance switching effects.
The non-volatile characteristics and simple configuration enables the additional exploration of the resistive memory cell to be implemented in a wide range of different applications. In addition, the assignee is developing CMOS friendly fabrication processes such that the RRAM can be manufactured on top of CMOS logic.
From the above, an RRAM device has been introduced as a new semiconductor device structure. In the RRAM device, since the number of program/erase (PE) cycles a memory cell can perform before becoming unreliable is limited, data should be arranged such that program/erase (i.e., write) operations are evenly spread across all locations in the RRAM device. This technique is called “wear leveling.”